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lipingx's avatar
lipingx
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

how do timing constraint for I2c bus

In my design, I used system clk = 3.125MHz to realize I2c SCL,SDA 200K i2c bus. I used counter in the verilog, so both SCL and SDA are treated as data line. Then, how to do timing contraint? ...
  • Nurina's avatar
    Nurina
    3 years ago

    Hello,


    Sorry for the late response. You may use set_max_delay instead of set_input_delay since the I2C is pretty slow. You may use below constraint, this is the typical values used.


    set_max_delay -from [get_ports {eeprom_scl}] 50

    set_min_delay -from [get_ports {eeprom_scl}] 0

    set_max_delay -from [get_ports {eeprom_sda}] 50

    set_min_delay -from [get_ports {eeprom_sda}] 0



    Regards,

    Nurina


Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to https://supporttickets.intel.com , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey


Regards,

Nurina