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Occasional Contributor

3 years ago

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how do timing constraint for I2c bus

In my design, I used system clk = 3.125MHz to realize I2c SCL,SDA 200K i2c bus. I used counter in the verilog, so both SCL and SDA are treated as data line. Then, how to do timing contraint? ...

Nurina
3 years ago
Hello,

Sorry for the late response. You may use set_max_delay instead of set_input_delay since the I2C is pretty slow. You may use below constraint, this is the typical values used.

set_max_delay -from [get_ports {eeprom_scl}] 50
set_min_delay -from [get_ports {eeprom_scl}] 0
set_max_delay -from [get_ports {eeprom_sda}] 50
set_min_delay -from [get_ports {eeprom_sda}] 0

Regards,
Nurina

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Regular Contributor

3 years ago

Hi,

In this case you just need to add set_input_delay to the eeprom_scl & eeprom_sda ports.

You also need a virtual clock to describe the eeprom_scl (I'm assuming this is a clock): https://www.intel.com/content/www/us/en/docs/programmable/683243/22-3/creating-virtual-clocks.html

You may find below documents useful:

https://www.intel.com/content/www/us/en/docs/programmable/683243/22-3/input-constraints-set-input-delay.html

https://www.intel.com/content/www/us/en/docs/programmable/683103/21-3/generating-initial-i-o-timing-data-for-fpgas.html

Regards,

Nurina

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Occasional Contributor

3 years ago

why use virtual clock?

why not use system clk = 3.125MHz?