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lipingx
Occasional Contributor
Occasional Contributorhow do timing constraint for I2c bus
In my design, I used system clk = 3.125MHz to realize I2c SCL,SDA 200K i2c bus.
I used counter in the verilog, so both SCL and SDA are treated as data line.
Then, how to do timing contraint?
...
Hello,
Sorry for the late response. You may use set_max_delay instead of set_input_delay since the I2C is pretty slow. You may use below constraint, this is the typical values used.
set_max_delay -from [get_ports {eeprom_scl}] 50
set_min_delay -from [get_ports {eeprom_scl}] 0
set_max_delay -from [get_ports {eeprom_sda}] 50
set_min_delay -from [get_ports {eeprom_sda}] 0
Regards,
Nurina
Nurina
Regular Contributor
Regular ContributorHello,
Are you using any IP for this I2C (e.g. HPS)? If no, you will have to apply timing constraints based on the timing violations reported by Timing Analyzer.
Regards,
Nurina
- lipingx
No IP was used.
Could you give suggestion based on my attached code?
Both SDA and SCL are handled by system clock.
