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lipingx's avatar
lipingx
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
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how do timing constraint for I2c bus

In my design, I used system clk = 3.125MHz to realize I2c SCL,SDA 200K i2c bus. I used counter in the verilog, so both SCL and SDA are treated as data line. Then, how to do timing contraint? ...
  • Nurina's avatar
    Nurina
    3 years ago

    Hello,


    Sorry for the late response. You may use set_max_delay instead of set_input_delay since the I2C is pretty slow. You may use below constraint, this is the typical values used.


    set_max_delay -from [get_ports {eeprom_scl}] 50

    set_min_delay -from [get_ports {eeprom_scl}] 0

    set_max_delay -from [get_ports {eeprom_sda}] 50

    set_min_delay -from [get_ports {eeprom_sda}] 0



    Regards,

    Nurina


Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,


Sorry for the late response. You may use set_max_delay instead of set_input_delay since the I2C is pretty slow. You may use below constraint, this is the typical values used.


set_max_delay -from [get_ports {eeprom_scl}] 50

set_min_delay -from [get_ports {eeprom_scl}] 0

set_max_delay -from [get_ports {eeprom_sda}] 50

set_min_delay -from [get_ports {eeprom_sda}] 0



Regards,

Nurina