SYiwe
Occasional Contributor
6 years agoHow can I eliminate negative slack in RapidIO IP Core
Hi,
In my design there's a 5G 4X Rapid IO IP Core. A single TX PLL is instantiated to drive
tx_bonding_clock_ch0~3.
I've tried to drive the sysclk signal with txclk(output from the RapidIO IP Core) and a
250MHz clock(output from a IO_PLL IP Core), both of the two cases got negative setup slacks
after timing analysis, which result in error data in rapidio packet, as you can see in the
following screenshot.
The frequency of reference clock is 100MHz.
Any suggestions?
Thanks, regards.