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SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

How can I eliminate negative slack in RapidIO IP Core

Hi, In my design there's a 5G 4X Rapid IO IP Core. A single TX PLL is instantiated to drive tx_bonding_clock_ch0~3. I've tried to drive the sysclk signal with txclk(output from the RapidIO IP Cor...
Nathan_R_Intel's avatar
Nathan_R_Intel
Icon for Contributor rankContributor
6 years ago

Hie,

Yes, please send your design to my email address nathan.ramachandran@intel.com

Anyway from your latest description, I am able to identify some incorrect clock connection information. syslck is the avalon sysclk. Connecting to tx_clk (which is sourced from transceiver PLL) is not recommended. Hence, please connect to IO PLL IP core. Also ensure the recommended frequency for sysclk is met. Currently you seem to be suing 250MHz which does not meet the maximum recommended frequency .Its documented in Table 16 of the RapidIO User Guide below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_rapidio.pdf

Please update your clock connections following the user guide.

Regards,

Nathan