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SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

How can I eliminate negative slack in RapidIO IP Core

Hi, In my design there's a 5G 4X Rapid IO IP Core. A single TX PLL is instantiated to drive tx_bonding_clock_ch0~3. I've tried to drive the sysclk signal with txclk(output from the RapidIO IP Cor...
Nathan_R_Intel's avatar
Nathan_R_Intel
Icon for Contributor rankContributor
7 years ago
Hie, From your description alone, I cannot determine what is causing the timing error. Could you attach your design achieve (.qar), together with which Quartus version used for me to help you with this error. Regards, Nathan
  • SYiwe's avatar
    SYiwe
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago

    Thanks.

    Can you give me an email address so I can send my design to you?

    Regards.