High speed 16b paralell bus to DSP

Question

Hello, i am quite new with FPGA, and need ideas how to solve my problem.

I have 128 points CCD, and i control detector as well as ADC from FPGA. FPGA connects to DSP processor by standard SRAM bus (DATA[15..0], CS#, RD#,WR#,ACK). CCD sensor is sampled at 30MHz, and i need to read data to DSP to do complex math with it. Original idea was to use FIFO, but DSP don't have correct interface ( to be more precise, it does not have CLK )

Any idea how to make it work ? Bus must have as low latency possible ( since it should push 480Mbps)

Data acquisition module was developed inside schematic/diagram programming, since i have little knowledge in VHDL.

Any suggestion would be appreciated

altera_forum · Answer

--- Quote Start ---

Hello, i am quite new with FPGA, and need ideas how to solve my problem.

I have 128 points CCD, and i control detector as well as ADC from FPGA. FPGA connects to DSP processor by standard SRAM bus (DATA[15..0], CS#, RD#,WR#,ACK). CCD sensor is sampled at 30MHz, and i need to read data to DSP to do complex math with it. Original idea was to use FIFO, but DSP don't have correct interface ( to be more precise, it does not have CLK )

Any idea how to make it work ? Bus must have as low latency possible ( since it should push 480Mbps)

Data acquisition module was developed inside schematic/diagram programming, since i have little knowledge in VHDL.

Any suggestion would be appreciated

--- Quote End ---

What DSP are you using and which Altera FPGA?

altera_forum · Answer

ADSP-21489 a bit oerclocked to match project needs (5MB SRAM, 600MHz clk)

Altera Cyclone 4 EP4CE6F17C6

Idea for now is this, will run trial with dsp and see how it goes (project attached, note that adc have 7 cycles delay, whats why i keeping fifo disabled )

altera_forum · Answer

--- Quote Start ---

ADSP-21489 a bit oerclocked to match project needs (5MB SRAM, 600MHz clk)

Altera Cyclone 4 EP4CE6F17C6

Idea for now is this, will run trial with dsp and see how it goes (project attached, note that adc have 7 cycles delay, whats why i keeping fifo disabled )

--- Quote End ---

It looks to me that the SDCLK pin could be active for the AMI SRAM interface too, internally it is used as the timing basis for the transfers. In case you have connected it you could try finding whether you could use one of the two edges to drive the rdclk of your fifo. Then it will run at 33 Ms/s or so. In case you haven't you will have to catch the read pulse with a high-speed internal clock (233 MHz or so). The AMI would then have to run a minimum of 4 clocks (adding 1 Waitstate) to extend the read pulse over two clocks, giving you the chance to catch it and present the output data in time. That would bring the transfer rate down to 25 Ms/s.

altera_forum · Answer

Hi, DSP does have SDCLK for memory interface, but in order to get 30MHz read cycle, i have to overclock DSP. As a result, SDCLK is more than 250MHz and it is CMOS output, so i get only noise on that pin ( very small amplitude sinus wave, i try to use that as my clk, idea was to use counter with reset, when CS is low, counter should start count edges on SDCLK, and when is grater than 2 or 3 (since i have minimum 3 wait cycles as default in DSP) it should create rising edge, but in reality not. At low speed, like SDCLK is 100MHz or less, it would work. But that would defeat purpose of using DSP in first place, since DSP don't have fast io, but have mind blowing fast dsp instruction execution speed.

https://www.alteraforum.com/forum/attachment.php?attachmentid=8745

At least detector readout runs without a glitch with trigger input

Since i am doing single point DFT inside DSP, i know that it should be possible to do inside FPGA, but that is too advanced for me right now. I could create NIOS 2f Core, but that is too slow

altera_forum · Answer

Have you considered using the SHARC PDAP port?

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High speed 16b paralell bus to DSP

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