Honored Contributor
Honored ContributorHi, DSP does have SDCLK for memory interface, but in order to get 30MHz read cycle, i have to overclock DSP. As a result, SDCLK is more than 250MHz and it is CMOS output, so i get only noise on that pin ( very small amplitude sinus wave, i try to use that as my clk, idea was to use counter with reset, when CS is low, counter should start count edges on SDCLK, and when is grater than 2 or 3 (since i have minimum 3 wait cycles as default in DSP) it should create rising edge, but in reality not. At low speed, like SDCLK is 100MHz or less, it would work. But that would defeat purpose of using DSP in first place, since DSP don't have fast io, but have mind blowing fast dsp instruction execution speed.
https://www.alteraforum.com/forum/attachment.php?attachmentid=8745 At least detector readout runs without a glitch with trigger input Since i am doing single point DFT inside DSP, i know that it should be possible to do inside FPGA, but that is too advanced for me right now. I could create NIOS 2f Core, but that is too slow
