Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

High speed 16b paralell bus to DSP

Hello, i am quite new with FPGA, and need ideas how to solve my problem. I have 128 points CCD, and i control detector as well as ADC from FPGA. FPGA connects to DSP processor by standard SRAM ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

--- Quote Start ---

FIFO is only 6 word long. And i can't relay on fifo to store data, better way would be menage it from DSP in master configuration.

--- Quote End ---

I believe Analog Devices intends that you use the DMA controller to manage FIFO. Yes, doing it with software would be tricky.

If you truly want to hold off the FPGA, see the section on interprocessor synchronization in the appnote I linked to.