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ADSP-21489 a bit oerclocked to match project needs (5MB SRAM, 600MHz clk)
Altera Cyclone 4 EP4CE6F17C6
Idea for now is this, will run trial with dsp and see how it goes (project attached, note that adc have 7 cycles delay, whats why i keeping fifo disabled )
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It looks to me that the SDCLK pin could be active for the AMI SRAM interface too, internally it is used as the timing basis for the transfers. In case you have connected it you could try finding whether you could use one of the two edges to drive the rdclk of your fifo. Then it will run at 33 Ms/s or so. In case you haven't you will have to catch the read pulse with a high-speed internal clock (233 MHz or so). The AMI would then have to run a minimum of 4 clocks (adding 1 Waitstate) to extend the read pulse over two clocks, giving you the chance to catch it and present the output data in time. That would bring the transfer rate down to 25 Ms/s.
Honored Contributor
