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Honored Contributor
Honored ContributorHigh speed 16b paralell bus to DSP
Hello, i am quite new with FPGA, and need ideas how to solve my problem. I have 128 points CCD, and i control detector as well as ADC from FPGA. FPGA connects to DSP processor by standard SRAM ...
Altera_ForumHonored Contributor
Honored ContributorADSP-21489 a bit oerclocked to match project needs (5MB SRAM, 600MHz clk)
Altera Cyclone 4 EP4CE6F17C6 Idea for now is this, will run trial with dsp and see how it goes (project attached, note that adc have 7 cycles delay, whats why i keeping fifo disabled )
