Occasional Contributor
Super ContributorYou need the clock output of the PLL (done automatically with newer devices; derive_pll_clocks for older devices or written out as shown below), a generated clock on the clock output port, and a false path so there is only clock analysis and no data analysis on the clock output:
create_generated_clock -name pll_out -source [get_pins <FPGA pll reference clock input pin>] [get_pins <PLL output clock pin for clk_1>]
create_generated_clock -name clk_1 -source [get_pins <FPGA pll output clock pin for clk_1>] [get_ports clk_1]
set_false_path -to [get_ports clk_1]
Occasional ContributorThank you for responding!
I already have those constraints for the FPGA and they work as intended.
My main issue is with the CPLD constraints :
In the FPGA project, those create_generated_clock instructions will create the clk_1 output that is related to the ref_clk. How do I then "share/transfer" this information to the CPLD's constraints file? That is, the CPLD's input clk_1's phase offset compared to the ref_clk?
I tried "faking" this phase offset by using the -waveform argument for the CPLD's clk_1 input but the problem with this is that I don't know for sure what the phase offset is of the clock going out of the FPGA's clk_1 output.
In the FPGA's project, if I use the report_path instruction to get the delay to the clk_1 output, I only get the path delay between the PLL output and the clk_1 port. The PLL is using the "Direct" mode so there will be phase offset between its input reference (REF_CLK) and its output, and due to the routing, the PLL output to the clk_1 port.
Is it a "better" solution to forward the REF_CLK directly to the clk_1 output, since it's a port to port path, use the delay I get from the report to recreate the clock at the CPLD's clk_1 input?
Super ContributorYou keep mentioning "FPGA" and "CPLD" so I am assuming these are Intel/Altera devices.
For the CPLD, you could use set_clock_latency to specify the delay of the clock arriving at that device, but this is source synchronous so the create_clock coming in should be adjusted using -waveform as you mention, phase shifting from REF_CLK, which should be defined as a virtual clock.
create_clock -name REF_CLK -period <period of REF_CLK>
create_clock -name clk_1 -period <period> -waveform {<rise time> <fall time>} [get_ports <CPLD clk_1 port>]
