help please......frequency divider

There might be problem in this code (possibly typing error) since the process is active only when reset = '1'.

add else after it:

if reset = '1' then

....

....

else

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what is the function of Reset?

if i take out the reset what will happend?

i just want 1 input only....

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Maybe you should just take an 'incomplete' grade for this assignment.

what is the function of Reset?

if i take out the reset what will happend?

i just want 1 input only....

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i try the code already,it was successful :)but i dont really understand the waveform:(..what should i get for the output Q?

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You should get what you asked for in your first post...a signal that toggles at the requested clock frequency.

KJ

You should see it like clock signal (low one half period then high).

But your frequencies are too low for simulation (on 25MHz system clock) so you will probably just see no change on Q if simulation is that short.

The remedy is to wait for hours or days. Or try testing higher frequencies e.g. 1MHz, 100Khz, 10KHz.

The other alternative is (in hardware or even simulation) is to use frequency meter on Q signal (count up number of 25MHz clocks per period of Q) then leave it overnight covering all selections and check in early morning.

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if im using std_logic_vector type...how?

generic(n: natural :=25);

port( divCLK: in std_logic;

level:in std_logic_vector (3 downto 0);

Q: out std_logic);

end countersystem;

----------------------------------------------------

architecture behv of countersystem is

signal clkdiv: std_logic_vector(n-1 downto 0);

begin

process(divCLK)

begin

if rising_edge(divCLK) then

clkdiv <= clkdiv + 1;

end if;

Q<=clkdiv(24);

from this i can get 1Hz, but how to get 2Hz,3Hz and so on from these coding...

is it

Q<=clkdiv(23),Q<=clkdiv(22)...and so on?

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Something like this...not tested, but should get you nearly done. Homework assignment?

use ieee.numeric_std.all;

architecture rtl of countersystem is

signal Q_int: std_ulogic;

type arr_integer is array(natural range <>) of integer;

constant CLK_FREQ: integer := 25000000;

constant MAX_COUNTS: arr_integer(0 to 3) := (CLK_FREQ/2-1, CLK_FREQ/4-1, CLK_FREQ/6-1, CLK_FREQ/8-1);

-- Constants for 1 Hz, 2 Hz, 3 Hz, 4 Hz...others left for the reader. This array will need to be expanded to be 0 to 15 to match the number of possible levels selectable by 'level'...

signal Current_Count: natural range 0 to CLK_FREQ/2

begin

process(divCLK)

begin

if rising_edge(divCLK) then

if (Reset = '1') then -- You should add a reset to the entity

Current_Count <= MAX_COUNTS(to_integer(unsigned(level)));

Q_int <= '0';

if (Current_Count = 0) then

Current_Count <= MAX_COUNTS(to_integer(unsigned(level)));

Q_int <= not(Q_int);

else

Current_Count <= Current_Count - 1;

end if;

end if;

end process;

Q <= Q_int;

end rtl;

Simulate and test first.

Kevin Jennings

You can either count up or count down...

set maxcount to a value depending on your choice. Let counter go up from 0 to maxcount and back to zero. Then use msb of count as clockout.