--- Quote Start ---
if im using std_logic_vector type...how?
generic(n: natural :=25);
port( divCLK: in std_logic;
level:in std_logic_vector (3 downto 0);
Q: out std_logic);
end countersystem;
----------------------------------------------------
architecture behv of countersystem is
signal clkdiv: std_logic_vector(n-1 downto 0);
begin
process(divCLK)
begin
if rising_edge(divCLK) then
clkdiv <= clkdiv + 1;
end if;
Q<=clkdiv(24);
from this i can get 1Hz, but how to get 2Hz,3Hz and so on from these coding...
is it
Q<=clkdiv(23),Q<=clkdiv(22)...and so on?
--- Quote End ---
Something like this...not tested, but should get you nearly done. Homework assignment?
use ieee.numeric_std.all;
architecture rtl of countersystem is
signal Q_int: std_ulogic;
type arr_integer is array(natural range <>) of integer;
constant CLK_FREQ: integer := 25000000;
constant MAX_COUNTS: arr_integer(0 to 3) := (CLK_FREQ/2-1, CLK_FREQ/4-1, CLK_FREQ/6-1, CLK_FREQ/8-1);
-- Constants for 1 Hz, 2 Hz, 3 Hz, 4 Hz...others left for the reader. This array will need to be expanded to be 0 to 15 to match the number of possible levels selectable by 'level'...
signal Current_Count: natural range 0 to CLK_FREQ/2
begin
process(divCLK)
begin
if rising_edge(divCLK) then
if (Reset = '1') then -- You should add a reset to the entity
Current_Count <= MAX_COUNTS(to_integer(unsigned(level)));
Q_int <= '0';
if (Current_Count = 0) then
Current_Count <= MAX_COUNTS(to_integer(unsigned(level)));
Q_int <= not(Q_int);
else
Current_Count <= Current_Count - 1;
end if;
end if;
end process;
Q <= Q_int;
end rtl;
Simulate and test first.
Kevin Jennings
Honored Contributor
