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Honored ContributorHelp on Cyclone III DK Start kit 3c25n
Hi,
I am new to this FPGA world. I have done projects on 8051, so i am familiar with c language I am trying to blink four LEDs my code is as below.When i analysis and synthesis its showing error as below. --- Quote Start --- Error (10119): Verilog HDL Loop Statement error at led_prj.v(19): loop with non-constant loop condition must terminate within 250 iterations --- Quote End ---
module led_prj(clk,rst,led);
input clk,rst;
//input ps;
output led;
reg led;
reg count;
reg flag;
always@(posedge clk or negedge rst)
begin
if(~rst)begin
led <= 4'b1111;
flag<= 1'b0;
count <= 25'd0;
end
else begin
while(count <= 25'd0 || flag == 1'b1)begin
count <= count + 25'd1;
led<= 4'b0000;
flag<= 1'b0;
end
count<= count+25'd1;
while(count <= 25'd0)begin
count <= count + 25'd1;
led<= 4'b1111;
flag<= 1'b1;
end
end
endmodule
5 Replies
Altera_Forumyou dont need case statement, use ring counter
something like led[4:0] <= {led[0],led[3:1] }- Altera_Forum
Thanks.
If i want to blink LEDs in sequence one by one. Then i have to use Case statement! - Altera_Forum
Please declare
led as wire [eg: wire [3:0] led ; ] and use assign led <= count[24] ? 4'b0000 : 4'b1111 ; This will help you to reduce LE utilization by FPGA ------------------------------------------------------ You can acheive delay in different ways 1. change count[ n] n value 2. change clock (clk) frequency 3. use "# " -- Simulation only not synthesis . . . Regards Vinod P A - Altera_Forum
Hi Vinodpa,
Thanks for ur reply, I closed that @always block.Now the error is solved, But the logic is not working in above program, So tried as below method, its working. But i need to know how to give delays, longer delays. --- Quote Start --- always@(posedge clk or negedge rst) begin if(~rst)begin led <= 4'b1111; count <= 25'd0;end else begin count <= count + 25'd1; led <= count == 25'd0 ?(led == 4'b0000 ? 4'b1111 : 4'b0000) : led ; end end endmodule --- Quote End --- - Altera_Forum
Please check that all the begin is closed properly, I think you didn't closed always block :o
Please note : For better design practice please avoid loops(while,for etc) in a design, practice fsm coding all the best !!!
