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Honored Contributor
15 years agoPlease declare
led as wire [eg: wire [3:0] led ; ] and use assign led <= count[24] ? 4'b0000 : 4'b1111 ; This will help you to reduce LE utilization by FPGA ------------------------------------------------------ You can acheive delay in different ways 1. change count[ n] n value 2. change clock (clk) frequency 3. use "# " -- Simulation only not synthesis . . . Regards Vinod P A