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Altera_Forum
Honored Contributor
15 years agoHi Vinodpa,
Thanks for ur reply, I closed that @always block.Now the error is solved, But the logic is not working in above program, So tried as below method, its working. But i need to know how to give delays, longer delays. --- Quote Start --- always@(posedge clk or negedge rst) begin if(~rst)begin led <= 4'b1111; count <= 25'd0;end else begin count <= count + 25'd1; led <= count == 25'd0 ?(led == 4'b0000 ? 4'b1111 : 4'b0000) : led ; end end endmodule --- Quote End ---