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Altera_Forum's avatar
Altera_Forum
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15 years ago

Help needed! thx

hello, when i run my program as NiosII hardware in nios2 ide, the following error msg appeared:

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Pausing target processor: OK

Reading System ID at address 0x01203080: verified

Initializing CPU cache (if present)

OK

Downloading 00800000 ( 0%)

Downloading 00810000 (81%)

Downloaded 79KB in 1.3s (60.7KB/s)

Verifying 00800000 ( 0%)

Verify failed between address 0x800000 and 0x80FFFF

Leaving target processor paused

I dont know what happen. at that address is SDRAM. can anyone help me? thanks!

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Is it a custom FPGA project? Try to run a memory test from on-chip memory and test the sdram.

    You probably have a timing problem. Check the settings in the memory controller, that your clocks are properly declared in Timequest, that your input/outputs are properly constrained, that your design meet the timing requirements and that you provide a clock with the correct phase shift to the sdram.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    Where was the problem, cause I've got the same situation?

    --- Quote End ---

    I think, you should check the pin assignments of SDRAM. Were all the pins are located correctly?You should also check that some output pins of your SDRAM may be bidirectional.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I double checked pin assignments, sdram controller config and still my sdram doesn't work. I can attach some screenshots. Could someone looked at it then?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I found the solution. I had to use 2 clock signals from pll. One for sdram and one for fpga. Then it works.