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Altera_Forum's avatar
Altera_Forum
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15 years ago

Help for counter programme

Design a 4-bit up/down counter with synchronous counting and asynchronous master reset. Write a VHDL design description of the counter based on the following criteria:

a) The counter increments or decrements on a negative clock edge only if its active-LOW enable

b) The master reset (MR) is an active-HIGH input that resets the counter to 0000 state.

c) The count outputs are Q3Q2Q1Q0 where Q0 is the LSB and Q3 is the MSB.

d) For up counting, a LOW at the UP_DW input. A HIGH at UP_DW input causes the counter to decrement.

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    The people are not here to make the homework of students.

    If you have a problem with a specific part, explain what you did and where you are blocked.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    so far i have this but i am not sure if i am doing the right thing.

    library ieee;

    use ieee.std_logic_1164.all;

    use ieee.numeric_std.all;

    entity mini is

    port ( en, m_reset, updown, clk : in std_logic;

    q : out std_logic_vector (3 downto 0));

    end mini;

    architecture flow of mini is

    signal mini :unsigned (3 downto 0);

    begin

    process ( en, m_reset, updown, clk )

    begin

    if (en = '1' and m_reset = '1')

    then

    q <= "0000");

    elsif(en = '0' and m_reset = '1')

    then

    q <= "0000");
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    the enable has to be inside the clk edge detect for it to work properly.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    currently, you have set a reset whenever m_reset = '1', you have 2 if branches with enable in them, one for when enable is '1' and one when en is '0'. These branches are actually the same thing as the only important signal is m_reset = '1'.

    as for the clock, you want the following code: 

    
elsif rising_edge(clk) then
  if en = '1' then
    --check count direction and count
  end if;
end if;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    this is what i have so far .

    library ieee;

    use ieee.std_logic_1164.all;

    use ieee.numeric_std.all;

    entity mini is

    port ( en, m_reset, UP_DW, clk : in std_logic;

    q : out std_logic_vector (3 downto 0));

    end mini;

    architecture flow of mini is

    signal count_sig :unsigned (3 downto 0);

    begin

    process ( en, m_reset, UP_DW, clk )

    begin

    if (en = '1' and m_reset = '1')

    then

    count_sig <= "0000";

    elsif(en = '0' and m_reset = '1')

    then

    count_sig <="0000";

    elsif falling_edge (clk) and UP_DW = '0'

    then

    count_sig <= count_sig +1;

    elsif falling_edge (clk) and UP_DW = '1'

    then

    count_sig <= count_sig -1;

    end if;

    end process;

    q <= std_logic_vector (count_sig);

    end flow;

    how to make the altera board show hex from " A to F " ??