Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Help for counter programme

Design a 4-bit up/down counter with synchronous counting and asynchronous master reset. Write a VHDL design description of the counter based on the following criteria: a) The counter in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

the enable has to be inside the clk edge detect for it to work properly.