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Altera_Forum's avatar
Altera_Forum
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15 years ago

Help for counter programme

Design a 4-bit up/down counter with synchronous counting and asynchronous master reset. Write a VHDL design description of the counter based on the following criteria: a) The counter in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

currently, you have set a reset whenever m_reset = '1', you have 2 if branches with enable in them, one for when enable is '1' and one when en is '0'. These branches are actually the same thing as the only important signal is m_reset = '1'.

as for the clock, you want the following code: 


elsif rising_edge(clk) then
  if en = '1' then
    --check count direction and count
  end if;
end if;