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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

gritch noise

actually, I made a system with my FPGA.

that works fine.

after that I want to check signals inside.

so, I attached signal tap II on same system.

once I attach signal tap II.

the signal of results are broken.

logically, those two are same system.

one different is that once signal tapII is assigned, volume of LEs are increased.

this is not because of signal tap II itself, but it is because the logics which did not used are instanced to show result on signal tap II.

even so, logics are not changed, but the results are broken.

what is wrong with it?

I have heard of gritch noise.

I use binaly counter, like 20bits counter for many places.

do you think it effects to the system?

should I use gray counter?

by the way, my system works with 200MHz

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Is your design properly constrained and does it meet all timing requirements? When Signaltap probes changes the behaviour of a system, in most of the cases it is a timing problem.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    thank you for quick answer.

    I would like to ask you one more.

    I am not good at timing adjustment.

    (quite few knowledge of time quest timing analyzer)

    which way is fast to learn timing check / timing adjustment.

    this means that

    when QuartusII give me a report, I have no idea with the numbers.

    the red letter might be bad, bad how bad it is?

    and if I want to correct those, which parameter should I change?

    I want to learn those things.

    thanks anyway.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Before reading the report you need to define an sdc file that lists all your constraints. Most importantly all your clocks inputs and fast I/O. Only then you can start and reading the reports and find out how to solve the timing problems.

    There is a very good user guide here (http://www.alterawiki.com/wiki/timequest_user_guide) and you should be able to find some Timequest tutorials on the Altera website.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    thanks and thanks.

    I haven't read whole document yet(133 is too heavy).

    but it seems so good document.

    thanks for the information.

    I will thank to Ryan.