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Honored Contributor
Honored Contributorgritch noise
actually, I made a system with my FPGA. that works fine. after that I want to check signals inside. so, I attached signal tap II on same system. once I attach signal tap II. the sign...
Altera_ForumHonored Contributor
Honored ContributorBefore reading the report you need to define an sdc file that lists all your constraints. Most importantly all your clocks inputs and fast I/O. Only then you can start and reading the reports and find out how to solve the timing problems.
There is a very good user guide here (http://www.alterawiki.com/wiki/timequest_user_guide) and you should be able to find some Timequest tutorials on the Altera website.
