Honored Contributori am getting some glitiched in the outputs, i am not sure what is the reason of then glitich and how to get rid of them, the glitichs happen in the output that are not changing
Honored ContributorAre you driving the output from a combinatorial block? When the inputs to a combinatorial block change, the data propagates through the block and can cause glitches on the output prior to settling.
You can either inforce state mapping on your input to prevent this or put a register on the output. Creating state mappings and custom logic to prevent glitches doesn't always work because Quartus tends to optimize them out. Registering the output always works but you have to have a clock in your design and the output will be one clock cycle late.Honored Contributorthank you for the reply, you mean i should use a register for the output, i have 2 process the first one is for current state process( synchronous process) which is clocked process to detrmine the current state while the second process is for Next State and output Logic Process (combinational process) that does not have clcok ,
so what u mean , you want to make registered process for the output , so clock should be used as it is registred or what you mean exactelyHonored ContributorI mean put a D flip flop on your output.
Glitching output -> DFF -> Glitch free output Use the same clock that you are using for your state machine. The only draw back is that the output will be delayed by 1 clock cycle.Honored ContributorStandard Mealy or Moore FSM designs, e.g. the Quartus HDL templates don't register the output signals, resulting in glitches. You should register those signals, that are fed to output pins.
Another option to design the FSM in a single clocked process. All signals will be registered without specific means.Honored Contributori already added the clock to the senstivity list in the process that performs the outputs but i still have the glitches
Honored ContributorThe sensitivity list in your always statement does not do anything about glitches. You have to do something about either your state assignments or register the output.
Honored Contributoryes i do understand , but when i add the clock to the senstivity list in the process the responsible for the outputs, i have to
if (Reset='0') then elsif (Clk'event AND Clk='1') then case -- isHonored ContributorIf the outputs are already registered, the problem is apparently different from simple combitional logic glitches, then it's rather a FSM design problem. You can use SignalTap to trace inputs, state variables an doutputs of the FSM.
Honored Contributorcould you please let me know how to register my outputs and what is the diffrence between the registerd output and buffered outputs
Honored Contributorhow about posting more of yuor code?
