Glitch on DCLK during Active Serial Arria 10

I have a PCB with an Arria 10 that I'd like to support both passive serial and active serial config. I can successfully configure the Arria 10 via JTAG and passive serial, but I cannot successfully program the flash (Micron MT25QU512ABB8ESF) and boot in active serial mode.

To achieve this, I have a switche on the MSEL pins and have been trying to change them from MSEL{2,1,0} = 0,0,1 for Passive Serial and 0,1,1 for Active Serial. I also have a buffer IC (TI SN74AUC2G126) connected to a switch to allow DCLK to be either an input to or output from the Arria 10.

Looking at DCLK output with the Intel flash loader bitstream loaded via JTAG, I see a glitch on DCLK - see attached scope grab. After the flash loader program completes, it fails to verify. If I try to boot anyway, the nStatus toggles and the part starts trying to configure again. I assume this glitch on DCLK is causing my problem?

The scope grab is with infinite persistence on. The glitch moves around the high side of the clock signal. There are some clock pulses that do not have a glitch.

I have tried removing the buffer so that DCLK is only an input into the Arria 10 to remove propagation delays, but that hasn't removed the glitch on DCLK. I have inspected VCC (0.95 V), VCCH_GXB{L,R}, VCC_PLL, and VCCPGM (all 1.8V) with a differential probe at vias on the back of the FPGA and do not see any noise on the power rails.

When configured via JTAG or Passive Serial with our bitstream, all other aspects of the system work as expected, even when testing across in-spec voltage and temperature variations, including 6.25 GHz transceivers and 2000 MT/s DDR4 memory controller.

Any suggestions about how to configure via Active serial would be greatly appreciated! Thanks.