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BenUhing's avatar
BenUhing
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4 years ago

Glitch on DCLK during Active Serial Arria 10

I have a PCB with an Arria 10 that I'd like to support both passive serial and active serial config. I can successfully configure the Arria 10 via JTAG and passive serial, but I cannot successfully p...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


May I know if there is a reason that you are using a buffer switch to connect the DCLK signal? I suspect that your U503 device is causing the glitches.


If you look into Intel Arria 10 Development kit, we do not use any buffer or switches for the DLCK and just connect DCLK to both Passive Serial and Active Serial device directly. You may refer to https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/arria10/FPGA/A10GX_PCIE_E3p1.pdf.


  • BenUhing's avatar
    BenUhing
    Icon for New Contributor rankNew Contributor
    4 years ago
    That’s good to know. I will remove it from future revisions. However, I have depopulated the buffer from my PCB and run a short wire across its pads connecting DCLK to AS_DCLK and the glitch is still there. Can you think of anything else that might be causing it?