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BenUhing's avatar
BenUhing
Icon for New Contributor rankNew Contributor
4 years ago

Glitch on DCLK during Active Serial Arria 10

I have a PCB with an Arria 10 that I'd like to support both passive serial and active serial config. I can successfully configure the Arria 10 via JTAG and passive serial, but I cannot successfully p...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


When you are programming the flash from FPGA, the DCLK is coming from FPGA internal clock.