Honored ContributorFor a Cyclone IV: Does Gigabit ethernet need to be implemented using transceivers, or can it be implemented using the normal IO pins? The PHY that was selected for this implementation has four separate Tx/Rx pins, and needs to clock data in/out on both clock edges. It is not clear to me whether the standard IO will support this.
Honored ContributorHi,
For the Gigabit ethernet Xcvr stratix 4 and stratix will support upto 10 GigE. Thats too you have to use LVDS IO line for interface. LVCOM wont support. T&R, SureshaHonored ContributorI need to implement a 1 Gige on a Cyclone IV. It looks like I can either use a transceiver to implement a serial SGMII, or use standard IO to implement an RGMII. For the RGMII implementation, it is not clear to me whether there are restrictions on what IO pins I can use to connect to the PHY.
Honored ContributorThere are no restrictions for GMII or RGMII.
Honored ContributorHi,
The GMII and RGMII interfaces don't use LVDS. They are single ended and use much lower frequencies on a parrallel bus. They will use LVCMOS bus: TMS320C6472/TMS320TCI6486 for GMII TLK2226 for RGMII Interface.( For sample only). But in the case of DDIO(needs to clock data in/out on both clock edges), It wont support LVDS. T&R SureshaHonored ContributorThe ethernet PHY I was looking at using states that the single ended Tx and Rx data interfaces use a DDR scheme, i.e. data is presented on both clock edges. I'm still looking over the documentation, but it is not clear to me whether the Cyclone IV supports this.
Honored ContributorHi,
As you have single ended Tx and Rx then better u can choose LVCMOS,DDIO. But In Cyclone IV if the LVCMOS IO standard support 1GigE data rate, you can surely go ahead.But i am sure it will support. T&R sureshaHonored ContributorCyclones do support DDR I/O.
You should check if the FPGA supports the speeds you need with the I/O standard you need though.Honored ContributorI agree Cyclone will support DDR IO, But the question is whether LVCMOS will 1 GigE data rate?
T&R sureshaHonored Contributor1x1 Gbit/s, no.
But 4x250 Mbit/s for a RGMII it will.Honored ContributorThere is absolutely no problem driving a GMII/RGMII interface with a Cyclone IV, using LVCMOS DDR I/O, and any pin can be used for them. If possible it is better to use a dedicated clock input for the receive clock as it will make meeting timing requirements easier. You can also use a pll output pin for the transmit clock but I don't think it's absolutely necessary.
The cyclone iii development kit (http://www.altera.com/products/devkits/altera/kit-cyc3.html) uses a RGMII interface to a Marvel PHY, you can have a look at the schematic to see how they did it.
