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Altera_Forum
Honored Contributor
Honored Contributorgigabit ethernet
For a Cyclone IV: Does Gigabit ethernet need to be implemented using transceivers, or can it be implemented using the normal IO pins? The PHY that was selected for this implementation has four separa...
Altera_ForumHonored Contributor
Honored ContributorThe ethernet PHY I was looking at using states that the single ended Tx and Rx data interfaces use a DDR scheme, i.e. data is presented on both clock edges. I'm still looking over the documentation, but it is not clear to me whether the Cyclone IV supports this.
