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Altera_Forum's avatar
Altera_Forum
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13 years ago

Generating a signal with noise

What i am doing is i am trying to do is add random numbers to a signal to find PSD later. I wrote a code for random numbers generator which is working fine shown below:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY random IS ------> Interface

GENERIC (n : INTEGER := 32); -- Input bit width

PORT( clk : IN STD_LOGIC;

random_num : OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0)

);

END random;

ARCHITECTURE Behavioral of random is

BEGIN

PROCESS(clk)

VARIABLE rand_temp : STD_LOGIC_VECTOR(n-1 DOWNTO 0) := (n-1 => '1' , OTHERS => '0');

VARIABLE temp : STD_LOGIC := '0';

BEGIN

IF(RISING_EDGE(clk)) THEN

temp := rand_temp(n-1) XOR rand_temp(n-2);

rand_temp(n-1 DOWNTO 1) := rand_temp(n-2 DOWNTO 0);

rand_temp(0) := temp;

END IF;

random_num <= rand_temp;

END PROCESS;

END;

After that i tried to add the random signal to a known signal to get a new signal so i can find PSD. I wrote a code for that and i am getting some errors. The code is

PACKAGE n_bit_int IS-- User-defined type

SUBTYPE BITS32 IS INTEGER RANGE -2**32 TO 2**32-1; -- -256 ~255

SUBTYPE BITS33 IS INTEGER RANGE -2**33 TO 2**33-1; -- -512 ~511

END PACKAGE n_bit_int;

LIBRARY WORK;

USE WORK.n_bit_int.ALL;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.MATH_REAL.ALL;

ENTITY cumulants IS

GENERIC (n : INTEGER := 32);

PORT( clk : IN STD_LOGIC;

x0 : IN BITS32;

x1 : IN BITS32;

x2 : IN BITS32;

x3 : IN BITS32;

y0 : OUT BITS33;

y1 : OUT BITS33;

y2 : OUT BITS33;

y3 : OUT BITS33

);

END ENTITY cumulants;

ARCHITECTURE Behavioral of cumulants is

COMPONENT random

PORT( clk : IN STD_LOGIC;

random_num : OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0)

);

END COMPONENT random;

BEGIN

PROCESS

VARIABLE rand_temp : STD_LOGIC_VECTOR(n-1 DOWNTO 0);

BEGIN

u1 : PORT MAP ( clk => clk1, random => rand_temp );

y0 <= x0 + rand_temp;

y1 <= x1 + rand_temp;

y2 <= x2 + rand_temp;

y3 <= x3 + rand_temp;

END PROCESS;

END;

The errors are

Error (10500): VHDL syntax error at cumulants.vhd(49) near text "PORT"; expecting "(", or an identifier ("port" is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at cumulants.vhd(49) near text ";"; expecting ":=", or "<="

Please help me. Where am i going wrong.

22 Replies

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hi dave

    I think i got where i went wrong..if i have any problem i ll ask for you help. thanks

    Aditya...:)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hi DAVE

    I am trying to find the mean and variance for random generating function code shown below. I know how to calculate practically but not able to implement it can you please help me..

    LIBRARY IEEE;

    USE IEEE.STD_LOGIC_1164.ALL;

    USE IEEE.NUMERIC_STD.ALL;

    USE IEEE.STD_LOGIC_SIGNED.ALL;

    ENTITY random IS ------> Interface

    GENERIC (n : INTEGER := 16); -- Input bit width

    PORT( clk : IN STD_LOGIC;

    random_num : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0);

    random_sum: OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)

    );

    END random;

    ARCHITECTURE Behavioral of random is

    BEGIN

    PROCESS(clk)

    VARIABLE rand_temp : STD_LOGIC_VECTOR(n-1 DOWNTO 0) := (n-1 => '1' , OTHERS => '0');

    VARIABLE temp : STD_LOGIC := '0';

    VARIABLE sum : STD_LOGIC_VECTOR(n-1 DOWNTO 0) :=( OTHERS => '0');

    BEGIN

    IF(RISING_EDGE(clk)) THEN

    temp := rand_temp(n-1) XOR rand_temp(n-2);

    rand_temp(n-1 DOWNTO 1) := rand_temp(n-2 DOWNTO 0);

    rand_temp(0) := temp;

    sum := sum + rand_temp;

    END IF;

    random_num <= rand_temp;

    random_sum <= sum;

    END PROCESS;

    END;

    --ADI
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    I am trying to find the mean and variance for random generating function code shown below. I know how to calculate practically but not able to implement it can you please help me..

    --- Quote End ---

    The implementation depends on what you really want.

    For example, if you want the mean and RMS as a function of time, then you can implement a digital filter. The mean is the DC component, so if you have an update rate requirement of several seconds, then that specifies your sample rate, and hence the bandwidth of your digital filter.

    Alternatively, you can implement the averaging in software.

    Before diving into an FPGA implementation, you need to determine whether that is the appropriate solution, and whether the whole solution needs to be implemented in an FPGA, or whether there is some FPGA and some processor partitioning that would make more sense.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    the random function i generated is w(n) right with so the mean is 1/n(summation of w(n) from 0 to n) and variance is 1/n-1(summation of w(n) square from 0 to n). So how can i implement the averaging in software or in digital filter?? can you please elaborate??

    --ADI
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    What i am trying to to do is to generate auto regressive process.

    _adi
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    the random function i generated is w(n) right with so the mean is 1/n(summation of w(n) from 0 to n) and variance is 1/n-1(summation of w(n) square from 0 to n). So how can i implement the averaging in software or in digital filter?? can you please elaborate??

    --- Quote End ---

    Look at the moving average filter figure on slide 115.

    http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    What i am trying to to do is to generate auto regressive process.

    --- Quote End ---

    I have not designed this type of system before, however, briefly reading this entry

    http://en.wikipedia.org/wiki/autoregressive_model

    It might be possible to implement this type of system using an Infinite Impulse Response (IIR) filter.

    You'll have to do a little more research to see if that is true.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hi dave i implemented division in my code but its not working as it must can you tell me if my implementation is correct or not

    LIBRARY IEEE;

    USE IEEE.STD_LOGIC_1164.ALL;

    USE IEEE.NUMERIC_STD.ALL;

    --USE IEEE.NUMERIC_BIT.ALL;

    USE IEEE.STD_LOGIC_SIGNED.ALL;

    --USE IEEE.STD_LOGIC_UNSIGNED.ALL;

    ENTITY random IS ------> Interface

    GENERIC (n : INTEGER := 16); -- Input bit width

    PORT( clk : IN STD_LOGIC;

    random_num : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0);

    x : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0);

    random_mean: OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0);

    random_sum: OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)

    );

    END random;

    ARCHITECTURE Behavioral of random is

    SHARED VARIABLE sum : STD_LOGIC_VECTOR(n-1 DOWNTO 0) :=( OTHERS => '0');

    SHARED VARIABLE rand_temp : STD_LOGIC_VECTOR(n-1 DOWNTO 0) := (n-1 => '1' , OTHERS => '0');

    SHARED VARIABLE count,count1: STD_LOGIC_VECTOR(n-1 DOWNTO 0) :=( OTHERS => '0');

    SIGNAL adi : STD_LOGIC_VECTOR(n-1 DOWNTO 0);

    SIGNAL sita : INTEGER RANGE 0 TO 2**n-1;

    SIGNAL count2,sum1 : INTEGER RANGE 0 TO 2**n-1;

    BEGIN

    PROCESS(clk)

    VARIABLE temp : STD_LOGIC := '0';

    BEGIN

    IF(RISING_EDGE(clk)) THEN

    temp := rand_temp(n-1) XOR rand_temp(n-2);

    rand_temp(n-1 DOWNTO 1) := rand_temp(n-2 DOWNTO 0);

    rand_temp(0) := temp;

    END IF;

    random_num <= rand_temp;

    END PROCESS;

    PROCESS

    BEGIN

    WAIT UNTIL clk = '1';

    sum := sum + rand_temp;

    count := STD_LOGIC_VECTOR(UNSIGNED(count) + 1);

    FOR I IN 0 TO n-1 LOOP

    count1(I) := count(n-1-I);

    END LOOP;

    count2 <= TO_INTEGER( UNSIGNED(count1));

    sum1 <= TO_INTEGER(UNSIGNED(sum));

    sita <= sum1 / count2;

    adi <= STD_LOGIC_VECTOR(TO_UNSIGNED(sita,16));

    END PROCESS;

    x <= count1;

    random_sum <= sum;

    random_mean <= adi;

    END;

    Regards

    Adi
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Can you define "its not working as it must"?

    --- Quote End ---

    Hey the division part the output i m getting is wrong...according to calculation it should be some value but after execution there are certain values which are repeating and zeros values are also seen in the division..is it because the division is hard to synthesize i am getting unexpected values???