Generating a signal with noise

What i am doing is i am trying to do is add random numbers to a signal to find PSD later. I wrote a code for random numbers generator which is working fine shown below:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY random IS ------> Interface

GENERIC (n : INTEGER := 32); -- Input bit width

PORT( clk : IN STD_LOGIC;

random_num : OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0)

);

END random;

ARCHITECTURE Behavioral of random is

BEGIN

PROCESS(clk)

VARIABLE rand_temp : STD_LOGIC_VECTOR(n-1 DOWNTO 0) := (n-1 => '1' , OTHERS => '0');

VARIABLE temp : STD_LOGIC := '0';

BEGIN

IF(RISING_EDGE(clk)) THEN

temp := rand_temp(n-1) XOR rand_temp(n-2);

rand_temp(n-1 DOWNTO 1) := rand_temp(n-2 DOWNTO 0);

rand_temp(0) := temp;

END IF;

random_num <= rand_temp;

END PROCESS;

END;

After that i tried to add the random signal to a known signal to get a new signal so i can find PSD. I wrote a code for that and i am getting some errors. The code is

PACKAGE n_bit_int IS-- User-defined type

SUBTYPE BITS32 IS INTEGER RANGE -2**32 TO 2**32-1; -- -256 ~255

SUBTYPE BITS33 IS INTEGER RANGE -2**33 TO 2**33-1; -- -512 ~511

END PACKAGE n_bit_int;

LIBRARY WORK;

USE WORK.n_bit_int.ALL;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.MATH_REAL.ALL;

ENTITY cumulants IS

GENERIC (n : INTEGER := 32);

PORT( clk : IN STD_LOGIC;

x0 : IN BITS32;

x1 : IN BITS32;

x2 : IN BITS32;

x3 : IN BITS32;

y0 : OUT BITS33;

y1 : OUT BITS33;

y2 : OUT BITS33;

y3 : OUT BITS33

);

END ENTITY cumulants;

ARCHITECTURE Behavioral of cumulants is

COMPONENT random

PORT( clk : IN STD_LOGIC;

random_num : OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0)

);

END COMPONENT random;

BEGIN

PROCESS

VARIABLE rand_temp : STD_LOGIC_VECTOR(n-1 DOWNTO 0);

BEGIN

u1 : PORT MAP ( clk => clk1, random => rand_temp );

y0 <= x0 + rand_temp;

y1 <= x1 + rand_temp;

y2 <= x2 + rand_temp;

y3 <= x3 + rand_temp;

END PROCESS;

END;

The errors are

Error (10500): VHDL syntax error at cumulants.vhd(49) near text "PORT"; expecting "(", or an identifier ("port" is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at cumulants.vhd(49) near text ";"; expecting ":=", or "<="

Please help me. Where am i going wrong.