Altera_Forum
Honored Contributor
Honored Contributorgenerate clock with pll
Hi,
I'd like to know how to generate a clock with the PLL to obtain two frequencies 8kHz and 256khz and simulate with ModelSim altera in cpld.thanksForum Discussion
11 Replies
Altera_ForumI don't think you can use an Altera PLL with that low a frequency.
You could use a PLL locked to, and generating, a higher frequency and divide down to 8KHz and 256KHz with logic. It depends what your input clock frequency is.- Altera_Forum
FPGA PLLs can't generate that low frequencies, check the respective device handbooks for the available PLL frequency range. Also CPLDs have no PLL hardware.
A clock divider is the usual solution for low frequencies. - Altera_Forum
ok thank you but how can I do to solve this problem I am beginner and I want a document that may help
- Altera_Forum
What is the frequency of your input clock?
8KHz is a nice divide of 256KHz (/32) so this is just 8 divide by 2s. A divide by 2 is a simple flip flop with the inverse of the output as the input. If your can choose an input frequency that is power of 2 multiple of 256KHz then it should be easy - Altera_Forum
I have not a specific input frequency, but I have to choose a frequency that I realized the two frequencies that I want.
- Altera_Forum
So how should we do with the details please and thanks
- Altera_Forum
Have a look at
http://www.fpga-faq.com/faq_pages/0019_divide_clock_by_n_point_5.htm. It should help Google "clock divider fpga" for more info! - Altera_Forum
ok but what I see is only a description
- Altera_Forum
What is it exactly you are after?
Do you need help using Quartus/Altera FPGAs? Do you need more info on clock dividers? The link I posted does have some Verilog code and I thought it gave a good introduction. Do you want someone to code the VHDL/verilog etc for you? It would be far better to read up on the subject and do the design and code it yourself. You'd learn a lot more and it might be fun :) Sorry to be a bit blunt but I am not sure what you are after. - Altera_Forum
Thank you, this is a way to learn .But I have a project or I do PRODUCING A synchronous clock generator using Altera CPLD max3, ie from an input clock I must have output frequencies 8kHz output and 256 kHz and I think I can utiliset altpll of Quartus (megawizard) but I also need the VHDL code and testbench to simulate in ModelSim-Altera.
in fact it was what I do.thanks
