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Altera_Forum
Honored Contributor
Honored Contributorgenerate clock with pll
Hi, I'd like to know how to generate a clock with the PLL to obtain two frequencies 8kHz and 256khz and simulate with ModelSim altera in cpld.thanks
Altera_ForumHonored Contributor
Honored ContributorHave a look at
http://www.fpga-faq.com/faq_pages/0019_divide_clock_by_n_point_5.htm. It should help Google "clock divider fpga" for more info!
