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Altera_Forum's avatar
Altera_Forum
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17 years ago

generate clock with pll

Hi, I'd like to know how to generate a clock with the PLL to obtain two frequencies 8kHz and 256khz and simulate with ModelSim altera in cpld.thanks
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

What is it exactly you are after?

Do you need help using Quartus/Altera FPGAs?

Do you need more info on clock dividers? The link I posted does have some Verilog code and I thought it gave a good introduction.

Do you want someone to code the VHDL/verilog etc for you? It would be far better to read up on the subject and do the design and code it yourself. You'd learn a lot more and it might be fun :)

Sorry to be a bit blunt but I am not sure what you are after.