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Altera_Forum
Honored Contributor
Honored Contributorgenerate clock with pll
Hi, I'd like to know how to generate a clock with the PLL to obtain two frequencies 8kHz and 256khz and simulate with ModelSim altera in cpld.thanks
Altera_ForumHonored Contributor
Honored ContributorFPGA PLLs can't generate that low frequencies, check the respective device handbooks for the available PLL frequency range. Also CPLDs have no PLL hardware.
A clock divider is the usual solution for low frequencies.
