Functional simulation vs Timing

Hi,

I'm trying to plan an entity that recieves 2 6 bits words and decides if there are 3 or more different bits between those two words. If there are 3 or more bits that differs - the output turns to '1'.

I simulated the device in "Functional" mode and it did exactly what I thought it should do, but in timing mode simulation - it simply don't turn c to '1' at all.

Can someone please assist ?

here is the code:

Library ieee;

Use ieee.std_logic_1164.ALL;

use IEEE.std_logic_unsigned.all;

-- This entity detects if there are more then 3 changes

-- between 2 6bits inputs.

Entity change3 is

port (

-- inputs

async_reset : in std_logic;

clock : in std_logic;

a,b : in std_logic_vector(5 downto 0);

-- output

c : buffer std_logic);

end change3;

Architecture rtl of change3 is

begin

process (clock,async_reset)

variable x: std_logic_vector (2 downto 0) :="000";

begin

if (async_reset='1') then

c <='0';

x:="000";

elsif (clock'event and clock='1') then

x:=x+(a(0) xor b(0));

x:=x+(a(1) xor b(1));

x:=x+(a(2) xor b(2));

x:=x+(a(3) xor b(3));

x:=x+(a(4) xor b(4));

x:=x+(a(5) xor b(5));

end if;

if (x>"010") then c<='1'; -- there are at least 3 different bits

else c<='0';

end if;

--end if;

end process;

end rtl;