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Honored Contributor
Honored ContributorFunctional simulation vs Timing
Hi, I'm trying to plan an entity that recieves 2 6 bits words and decides if there are 3 or more different bits between those two words. If there are 3 or more bits that differs - the output turns...
Altera_ForumHonored Contributor
Honored Contributorif RTL simulation doesn't match gate level, you should make sure you've applied timing constraints to the design, then check your timing report. if you meet a longer period than the clock you're using in the timing simulation, the timing simulation results won't match the expected (RTL simulation) results.
i don't think any registers will be inferred from your snippet, the code looks all combinatorial. is this what you expected?
