FTDI FT2232H Sync FIFO + FPGA

Hi guys,

I'm using Morph-IC II and i'm having problems establishing the usb-communication between my Cyclone 2 and the FTDI FT2232H.

My objective is to send a start/reset signal from PC->FPGA, then access the data from the FPGA till an end/reset signal.

My problem is now the combination of sending/receiving.

I configured the FTDI in Synchronous FIFO Mode(getting the 60MHz clk) and it works fine when i send only in 1 direction.

This task has not to be parallel,it should go like this:

PC->START->FPGA switch to read

FPGA->DATA->PC switch to write

PC->STOP->FPGA

(VHDL)

To achieve this I have a state machine for sending and one for receiving. These 2 are working fine when i only use one and comment out the other...

By the way,if I comment out only the line where i access the data it works also,but without data not very useful^^

I dont know exactly how i should switch between the write/read state machines...right now i react on RXF low,which indicates that the FTDI(PC)

has data to send,because the PC sends only start/stop/reset-commands,i prefer these.

On PC(C#) side I use the D2XX-drivers. Init the Module and use SetBitMode to go into Synchronous FIFO,then read/write with the FTDI-functions.

I've read something about configuring the data-pins as in/output with the SetBitMode-Mask,but i didn't made progress using this.

Has anyone of you done this before and can help me? Is it possible to serial read/write in this mode or only 1 direction possible?

Any hints are welcome :), if you need more informations,code,... just say

Thank you very much for help,

Best Regards,

Andreas

15 Replies

Altera_Forum
Honored Contributor
12 years ago
Hi Andreas,

Here's my notes on interfacing to these devices

http://www.ovro.caltech.edu/~dwh/correlator/pdf/ftdi.pdf

I plan on posting the code eventually, however, I'm still hacking away on it when I get time ...

Cheers,
Dave
- hon1
  New Contributor
  1 year ago
  Hi Dave,
  I hope to learn from your notes on interfacing the FTDI chip but the link is not working. Possible for you to post your notes again?
  Best,
  Hon
Altera_Forum
Honored Contributor
12 years ago
Thank you,I will read through your document,hope I find help there

any other suggestions?

--> Working now,thank you for help!!!
Altera_Forum
Honored Contributor
11 years ago
Hi Dave/Stylopath,

since I'm planning to use exactly this setup, do you mind sharing your source? I really don't want to re-invent the wheel.

regards,
Günther
Altera_Forum
Honored Contributor
11 years ago
Hi Günther,

--- Quote Start ---

since I'm planning to use exactly this setup, do you mind sharing your source? I really don't want to re-invent the wheel.

--- Quote End ---

Sure.

How familiar are you with Qsys and IP cores?

Do you have a top-level design for your FPGA project yet, eg., a top-level entity and a pin assignments script? If you do, sent it to me, and I'll create a dummy project with a Qsys system and the bridge included. That'll allow me to ensure that I've included all the correct files.

Cheers,
Dave
Altera_Forum
Honored Contributor
11 years ago
Thanks Dave,

I got it working eventually. The design you sent me was for the asynchronous mode, but using the existing IP and your documentation, I could get the synchronous mode working as well.

Regards,
Günther
Altera_Forum
Honored Contributor
11 years ago
Hi Günther,

--- Quote Start ---

I got it working eventually. The design you sent me was for the asynchronous mode, but using the existing IP and your documentation, I could get the synchronous mode working as well.

--- Quote End ---

Excellent!

The FTDI to Avalon-MM bridge performance would be much higher using a binary protocol like that used with the JTAG-to-Avalon-MM bridge ...

https://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf
https://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.zip

But I haven't gotten around to writing that code ...

Cheers,
Dave
Altera_Forum
Honored Contributor
11 years ago
Hi Dave -

Is it possible you can share your VHDL/Verilog code for UM232H Synchronous FIFO mode.
Basically the blocks in FTDI Synchronous FIFO mode to Avalon-ST Bridge diagram ?
I just want to use those blocks for interfacing an FPGA for data transfer.

Thanks
JP

--- Quote Start ---
Hi Günther,

Excellent!

The FTDI to Avalon-MM bridge performance would be much higher using a binary protocol like that used with the JTAG-to-Avalon-MM bridge ...

https://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf
https://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.zip

But I haven't gotten around to writing that code ...

Cheers,
Dave
--- Quote End ---
Altera_Forum
Honored Contributor
11 years ago
Hi JP,

--- Quote Start ---

Is it possible you can share your VHDL/Verilog code for UM232H Synchronous FIFO mode.
Basically the blocks in FTDI Synchronous FIFO mode to Avalon-ST Bridge diagram ?
I just want to use those blocks for interfacing an FPGA for data transfer.

--- Quote End ---

Sure. I'm in the process of writing a MATLAB .mex interface to the binary version of the protocol, which will allow the highest performance. Once I get that working, I was going to update the documentation, and make sure the _hw.tcl files worked independently of my revision system, eg., an unzipped version of the library could be used directly.

If you want to use the current version of the code ASAP, just email me and I'll send you the code. If you want to wait until next week, I should have the code updated and documented. At that point, I'll post the code here, or on the Altera Wiki for all to use.

Cheers,
Dave
Altera_Forum
Honored Contributor
9 years ago
Dear Dave Hawkins,
let me first introduce myself.
I am Michele Ricci, a master degree student in electronic engineering at Politecnico di MIlano. I am currently working on my master thesis and one of my tasks is to interface a spartan6 with a FT232H chip in a 245 synchronous style. I' ve found on a altera forum a thread about this topic and i've seen the notes that you posted about it. I was wondering if you mind sharing with me your vhdl/verilog code for the communication (basically the blocks described at page 24 of your notes), that could really make my work easier and, most of all, faster.

Thank you in advance if you accept to do this, if not i must however thank you for the notes , wich i' ve found extremely detailed and clear.

Best Regards,

MIchele Ricci
Altera_Forum
Honored Contributor
9 years ago
Dear Dave Hawkins,
let me first introduce myself.
I am Michele Ricci, a master degree student in electronic engineering at Politecnico di MIlano. I am currently working on my master thesis and one of my tasks is to interface a spartan6 with a FT232H chip in a 245 synchronous style.I am wondering if you mind sharing with me your vhdl/verilog code for the communication (basically the blocks described at page 24 of your notes), that could really make my work easier and, most of all, faster.

Thank you in advance if you accept to do this, if not i must however thank you for the notes , wich i' ve found extremely detailed and clear.

Best Regards,

MIchele Ricci