FT2232H 245 Synchronous FIFO Mode problem

Hello

Im very new to FPGA's and am still learning so please be kind if the problem is obvious :)

i have a FT2232H set to 245 Synchronous FIFO Mode.

i have a program on the pc using the d2xx drivers sending exactly 512 bytes.

the problem is when the fpga receives these 512 bytes and places them into a ram block module i am using, every time i send the 512 bytes it seams to read in 2 empty bytes first then reads in the correct 512 offsetting every thing by 2 bytes. then the next frame i send every thing is offset by 4 bytes then 6 and so on

my code is very simple

it has 2 buffers that are 3072 bytes (im only using 512 at the moment)

it fills one then once that is full it swaps to the next one and fills that one.

another bit of code is reading the none filling buffer and cycling the data to a dot matrix display (this part of the design is ok and can be ignored)

below is the timing diagram for the 245 FIFI

http://img580.imageshack.us/img580/5303/ft2232htiming.jpg

i have attached my code. all dot matrix display update code can be ignored. the problem lies in the FIFO section.

apart from these extra 2 bytes every frame (causing the buffer to be offset by 2 bytes every frame) it seams to behave correctly.

CLK = 50mhz

fifo_clk = 60mhz from FT2232H

im not sure if its a timing fault or a fault in my state machine.

i have attached my verilog file

any help would be much appreciated or just to be pointed in the right direction :)

its so close to working just this one little problem!