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Honored ContributorFT2232H 245 Synchronous FIFO Mode problem
Hello
Im very new to FPGA's and am still learning so please be kind if the problem is obvious :) i have a FT2232H set to 245 Synchronous FIFO Mode. i have a program on the pc using the d2xx drivers sending exactly 512 bytes. the problem is when the fpga receives these 512 bytes and places them into a ram block module i am using, every time i send the 512 bytes it seams to read in 2 empty bytes first then reads in the correct 512 offsetting every thing by 2 bytes. then the next frame i send every thing is offset by 4 bytes then 6 and so on my code is very simple it has 2 buffers that are 3072 bytes (im only using 512 at the moment) it fills one then once that is full it swaps to the next one and fills that one. another bit of code is reading the none filling buffer and cycling the data to a dot matrix display (this part of the design is ok and can be ignored) below is the timing diagram for the 245 FIFI http://img580.imageshack.us/img580/5303/ft2232htiming.jpg i have attached my code. all dot matrix display update code can be ignored. the problem lies in the FIFO section. apart from these extra 2 bytes every frame (causing the buffer to be offset by 2 bytes every frame) it seams to behave correctly. CLK = 50mhz fifo_clk = 60mhz from FT2232H im not sure if its a timing fault or a fault in my state machine. i have attached my verilog file any help would be much appreciated or just to be pointed in the right direction :) its so close to working just this one little problem!15 Replies
Altera_ForumHi
I am having the same problem. So far, in my application, I can live with it, just dealing with the two extra bytes. However, I am curious if you figured out what the issue was? If so I would appreciate any advice you may have. Thanks Hans- Altera_Forum
yup the issue was the way i set up the hardware. i had to add a clk termination resister to stop signal bounce back :) the second i added this one resister it works perfect :)
- Altera_Forum
Hi
I assume that you are referring to the 60MHz clock coming from the FTDI chip to the FPGA? Thanks - Altera_Forum
yes :) thats correct
- Altera_Forum--- Quote Start --- yes :) thats correct --- Quote End --- I use morphic-ii from FTDI and the eeprom has channel A configured as FIFO 245. But, i can't see any clock(60MHz) in pin 32 of FT2232H. Is there any set we need to get 60MHz in pin 32 ? Is there any command to send by usb ?
- Altera_Forum--- Quote Start --- I use morphic-ii from FTDI and the eeprom has channel A configured as FIFO 245. But, i can't see any clock(60MHz) in pin 32 of FT2232H. Is there any set we need to get 60MHz in pin 32 ? Is there any command to send by usb ? --- Quote End --- you need some code like this to enable the clock FT_SetBitMode(ftHandle, 0xff, 0x40); '0x40 = Single Channel Synchronous 245 FIFO Mode (FT2232H and FT232H devices only)'
- Altera_Forum
Setbitmode works fine. But, i'd like to use this clock into fpga to my state machine.
In the schematic clkout pin is connected to FPGA J2 pin. My state machine is not running. I copy pin J2 to another pin (debug pin) to see the waveform in oscilloscope. The debug pin remains in zero level. Is pin clockout from FT2232H connected to FPGA J2 pin ? - Altera_Forum
i also wanted to use this as my fpga clock but seeing as its dead untill the pc enables it, its pretty much useless as a main clock :(
so i had to add another clock for my fpga - Altera_Forum
Could you give me more info on resistor value and where you have added it?
Thanks - Altera_Forum--- Quote Start --- Could you give me more info on resistor value and where you have added it? Thanks --- Quote End --- I only needed the resistor when breadboarding the projrct. Once on pcb it was not needed as the two ftdi/fpga where only a few mm from each other. On the breadboard I placed it as close to the fgpa clk input as I could. I cant remember the value, I think it was 100ohm.
