Honored ContributorI am connecting the Cyclone V PCIe Hard IP to the HPS SDRAM memory through an fpga2sdram avalon-mm 64-bit wide interface. This interface seems to look like 4 GB on the FPGA side, even though I only have 1 GB of ddr3 memory. Is there a way in qsys to configure how many address bits are used by the fpga2sdram interface, or will it always be 32?
Honored ContributorIt's always fixed to be 32-bit addresses regardless of how much memory is connected. One way you can limit the address space is by placing the address expansion bridge between your FPGA masters and the FPGA-to-SDRAM interface and just hardcode the window to live at 0x0000_0000 and setup the window size to match your memory depth.
Honored ContributorThanks for the info. BTW, I am using your modular sgdma ip in this design, since the latest version supports 64-bit addressing.
Honored ContributorAs a heads up with the latest version of Modelsim there is some RTL that will not simulate in the read master of that DMA engine. I wrote a quick fix for it but haven't had a chance to test it and that'll be a while so if you need to simulate it I can send you the verilog file that I believe will fix the problem. The issue only affects simulation, the hardware should continue to work fine (basically Mentor tightned up their verilog support in Modelsim so a minor update is needed to avoid the problematic line in the read burst logic).
Honored ContributorThanks for the heads up. I'm not planning to simulate your rtl, but I will keep your fix in mind, if I change mine. I understand and have experienced Mentor tightening up their verilog support.
