Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

FPGA2SDRAM Address Space Size

I am connecting the Cyclone V PCIe Hard IP to the HPS SDRAM memory through an fpga2sdram avalon-mm 64-bit wide interface. This interface seems to look like 4 GB on the FPGA side, even though I only h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

It's always fixed to be 32-bit addresses regardless of how much memory is connected. One way you can limit the address space is by placing the address expansion bridge between your FPGA masters and the FPGA-to-SDRAM interface and just hardcode the window to live at 0x0000_0000 and setup the window size to match your memory depth.