Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

FPGA2SDRAM Address Space Size

I am connecting the Cyclone V PCIe Hard IP to the HPS SDRAM memory through an fpga2sdram avalon-mm 64-bit wide interface. This interface seems to look like 4 GB on the FPGA side, even though I only h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thanks for the heads up. I'm not planning to simulate your rtl, but I will keep your fix in mind, if I change mine. I understand and have experienced Mentor tightening up their verilog support.