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Altera_Forum
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12 years ago

FPGA2SDRAM Address Space Size

I am connecting the Cyclone V PCIe Hard IP to the HPS SDRAM memory through an fpga2sdram avalon-mm 64-bit wide interface. This interface seems to look like 4 GB on the FPGA side, even though I only h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

As a heads up with the latest version of Modelsim there is some RTL that will not simulate in the read master of that DMA engine. I wrote a quick fix for it but haven't had a chance to test it and that'll be a while so if you need to simulate it I can send you the verilog file that I believe will fix the problem. The issue only affects simulation, the hardware should continue to work fine (basically Mentor tightned up their verilog support in Modelsim so a minor update is needed to avoid the problematic line in the read burst logic).