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Altera_Forum's avatar
Altera_Forum
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10 years ago

FPGA-to-HPS bridge, too slow?

Hi, my co-worker is using the Cyclone V with the embedded ARM cores. I often stop by his cube and ask him his opinion of the SoC. His biggest complaint is the FPGA-to-HPS bridge which he says is a big bottleneck. He admits that there may be some other knobs available to increase the throughput and make data transfers more deterministic but he hasn't found the knob. I thought to post this question and see the responses. I assume that when the Stratix 10 is released there wouldn't be such a bottleneck but I may be wrong. I'm still undecided about the embedded cores and am curious what applications it is best suited for. Can these cores, either on the Cyclone V or Stratix 10, compete with the multi-core DSPs from TI such as the TMS320C6678. All of my designs I have used a high-performance FPGA and a high-performance DSP. I'm waiting to see how things turn out before putting an SoC on my next design. I admit it is very exciting! Please let me know you comments. Thanks, joe

18 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    could you tell a little bit more about too slow means? maybe there is another configuration that causing you in slower speed?

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi and thanks for responding to my post. The FPGA will interface with a Analog Devices TigerSharc through its Link Ports. The FPGA side implements the Link Port Interface and then passes the received data to the HPS side. The time it takes to pass data from the FPGA side to the HPS side is very long and cannot keep up with the Link Port data rate.

    Is anyone else experiencing this type of behavior over the HPS bridge?

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi, how did you confirm if the data congestion is came from the side that is entering or exit the bridge? how did you measure the simulated data flow?

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi. I'm using mSGDMA in Cyclone V FPGA to read and write directly to shared memory. In between I plan to do data processing using Avalon-ST Interfaces. With this solution I now can process 350 MB/s. Actually CPU is only used to control DMAs. As comparison a simple memcpy requires 100% of CPU for less bandwidth. If You plan to use floating points in Your DSP applications then Arria10 might be more suitable because it has FP in hardware.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    Hi. I'm using mSGDMA in Cyclone V FPGA to read and write directly to shared memory. In between I plan to do data processing using Avalon-ST Interfaces. With this solution I now can process 350 MB/s. Actually CPU is only used to control DMAs. As comparison a simple memcpy requires 100% of CPU for less bandwidth. If You plan to use floating points in Your DSP applications then Arria10 might be more suitable because it has FP in hardware.

    --- Quote End ---

    your application also utilizing the bridges?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi, I use only lightweight bridge for configuring DMAs per Avalon-MM interface. I transfer data from FPGA directly to DDRAM without going to CPU. The CPU only waits for transfer to complete.

    If You add "Cyclone V Hard processor system" You can define that You want to have "FPGA-to-HPS SD-RAM interface" available so You get port f2h_sdram0_data in hps component. Then I connect DMAs mm_write/mm_read ports to f2h_sdram0_data.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    did you face any data congestion issue with the light weight bridge?

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    No, but my traffic on lw-bridge is low: writing about four hundred DMA descriptors per second, each 20 bytes or so. Is Your congestion permanent? or is it a small lag?

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    There is some small lag during peak transfer, but those mainly is due to the post data manipulation on the Arm core area, as my manipulation task priority is quite high.