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Altera_Forum
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10 years ago

FPGA-to-HPS bridge, too slow?

Hi, my co-worker is using the Cyclone V with the embedded ARM cores. I often stop by his cube and ask him his opinion of the SoC. His biggest complaint is the FPGA-to-HPS bridge which he says is a bi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi. I'm using mSGDMA in Cyclone V FPGA to read and write directly to shared memory. In between I plan to do data processing using Avalon-ST Interfaces. With this solution I now can process 350 MB/s. Actually CPU is only used to control DMAs. As comparison a simple memcpy requires 100% of CPU for less bandwidth. If You plan to use floating points in Your DSP applications then Arria10 might be more suitable because it has FP in hardware.