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Altera_Forum's avatar
Altera_Forum
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17 years ago

FPGA pin status while FPGA is configured

Hi Everyone,

Does anyone has experimented, what is FPGA pin status (except configuration pins) while it is being configured through any possible means (e.g. JTAG (SOF, JIC), AS (POF), etc.)?

I have tried to figure it out by probing few pins on one board (UP3) but it does not seem to be changed while configuration is loaded into FPGA, so is it the normal behavior or other pins toggles? Does anyone know better way to experiment it?

Thanks,

Ketan

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    May be I misunderstood the question, but pin state during configuration is exactly defined in device manuals (for all Altera FPGA, I think): All pins are set as input with weak pull-up from reset (POR respectively asserting NCONFIG) until start of user mode. Do you have any indication of a device behaving different?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thanks FvM! I do not have come across any situation where device is behaving differently. But as a precutionary act for our new board design I would like to know does any pin's signal level changes at time when configuration is loaded to FPGAs? Because we are having few sensitive parts on board which may get damaged if signal level of pin gets changed at the time of configuration. Anyways I am looking at device's datasheet but if there is any means to experiment/simulate above mentioned case then it would be great to me as I will get rid from any uncertainity.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I see. So, pins having an low idle level without pull-down resistor should be expected to change state. A usual means is to use a 2k pull-down resistor with pins that must maintain a low idle level during configuration.