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Altera_Forum
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18 years ago

FPGA pin status while FPGA is configured

Hi Everyone, Does anyone has experimented, what is FPGA pin status (except configuration pins) while it is being configured through any possible means (e.g. JTAG (SOF, JIC), AS (POF), etc.)? ...
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Altera_Forum
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18 years ago

May be I misunderstood the question, but pin state during configuration is exactly defined in device manuals (for all Altera FPGA, I think): All pins are set as input with weak pull-up from reset (POR respectively asserting NCONFIG) until start of user mode. Do you have any indication of a device behaving different?