FPGA pin status while FPGA is configured

Thanks FvM! I do not have come across any situation where device is behaving differently. But as a precutionary act for our new board design I would like to know does any pin's signal level changes at time when configuration is loaded to FPGAs? Because we are having few sensitive parts on board which may get damaged if signal level of pin gets changed at the time of configuration. Anyways I am looking at device's datasheet but if there is any means to experiment/simulate above mentioned case then it would be great to me as I will get rid from any uncertainity.