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Altera_Forum
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18 years ago

FPGA pin status while FPGA is configured

Hi Everyone, Does anyone has experimented, what is FPGA pin status (except configuration pins) while it is being configured through any possible means (e.g. JTAG (SOF, JIC), AS (POF), etc.)? ...
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Altera_Forum
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18 years ago

I see. So, pins having an low idle level without pull-down resistor should be expected to change state. A usual means is to use a 2k pull-down resistor with pins that must maintain a low idle level during configuration.